Thursday, April 09, 2015

Chicago and Midwest Tourism

Choose Chicagofamily and kids
Navy PierSeadog Cruises: Seadog Extreme, Speedboat Lake Tour, River & Lake Architectural Tour
Fermilab Fermilab, Rd a-1, Batavia, IL, United States

Chicago's North Shore Convention & Visitors Bureau
Visit Milwaukee

Greater Madison Convention and Visitors Bureau

Cedar Rapids

Quad Cities: Mississippi River Visitor CenterRock Island Locks & Dam 15
John Deere Factory Tour East Moline, IL
John Deere Pavilion

Wisconsin French Cheese
Wisconsin Cheese TraitsFrench list, Brie, Camembert, Neufchatel
MontChevre Belmont

Trek Bikes Factory Tour, Waterloo, WI
Harley Davidson Factory Tours Menomonee Falls Powertrain Operations
Miller Coors Brewery Tours Milwaukee Brewery Tour
SC Johnson Wax Visiting
Jelly Belly Wisconsin Warehouse Tours

Tour Loop Map

Sunday, March 29, 2015

Chinese Catholic Village

A Visit to China's Largest Catholic Village Shanxi Taiyuan Qinxu Qinyuan Liuhecun
山西省太原市清徐县清源镇六合村 Liuhe

Crossings Tea

Integrated Development Environment

Integrated development environmentComparison
Eclipse, all languages
NetBeans, Java, C/C++
Xcode, C/C++, Objective-C, Kava, Python, Ruby, Swift

Web integrated development environment
Cloud IDE rating
Comparison of JavaScript-based source code editors
Ace editor Microsoft Visual Studio
-- Cloud9 IDE - BitBucket, GitHub, 512MB mem, 1G disk, linter, completion, no python3-tk
-- Koding - GitHub, 1G mem, 3G disk, code..., terminal only, no run, no python3-tk
-- PythonAnywhere 512MB disk, no python3-tk
CodeMirror editor
-- Codenvy 512MB Eclipse - GitHub, Google+, code..., CodeMirror or Orion, python boot/run problem
-- SourceLair 512MB 1CPU, simple, no vi, emacs, 3 types of projects HTML/PHP, Django, Other, run and linter is python2, no keyword completion, no python3-tk
-- Codio (not free)


Thursday, March 19, 2015

EDA Acronyms Standards Development at Si2

  • Cadence DFII layout & schematic views
  • Open Access layout & schematic views
  • Milky-Way CEL, FRAM, ... views
  • Verilog
  • SystemVerilog(*)
  • Verilog AMS(*)
  • Tetramax
  • VHDL
  • Liberty NLDM
  • Liberty NLPM
  • Liberty NLNM
  • Liberty CCS - Composite Current Source
  • Liberty CCSN - Noise
  • Liberty ECSM - Effective Current Source Model
  • PLIB
  • Timing Library Format (.tlf)
  • LEF
  • DEF
  • SLIB
  • Oasis
  • SPEF
  • FastScan
  • STIL/CTL (Core Test Language)
  • UPF (Unified Power Format)
  • CPF (Common Power Format)
  • APL/RedHawk
  • AOCVM (Advanced On Chip Variability Model)
  • Wednesday, February 25, 2015